A FPGA Based Range Delay Active Radar Calibrator

This study reports design an active radar calibrator (ARC) that produces equal spacing point target responses that serve as control points for both geometric and radiometric calibrations. The delay is digitally controlled implemented by FPGA. Specification and performance of the digital ARC were tested on C-band ERS-2 SAR image. From the experimental results, the FPGA circuit can produce one to three calibration points of desired time delays. Compared to analog time delay, the current ARC generates delay error less than 10ns, greatly reduced from 30-50 ns that analogy time delay has. In addition, the stability of the time delay and output power in the FPGA based ARC are both much better than that of the analog delay version. Introduction Synthetic aperture radar (SAR) is capable of observing the changes of the earth surface in all weather. It has a great deal of the advantages to analyze and to collect the information about the environment on the earth, such as geological survey, the movement of the surface of the earth, and the ocean polluted extent, to name a few. However the precise geometric and radiometric calibrations are the essential for SAR image processing before qualitative and quantitative analysis can be made. Since 80’s, active radar calibrator was introduced for airborne and satellite SAR/scatterometer system field calibration[1][2][3][4]. Ulaby et al. presented a basic concept of ARC design[1]. In 1990, Daleman used range time delay technology in ARC system to get more echo point signal in SAR image[5]. Polarimetric ARC (PARC) system was developed for fully polarimetric SAR calibration[6]. A frequency shift ARC system used frequency shift to make some point signals along azimuthal track.[7] In recent years, fully digital controlled ARC was designed for high frequency and high resolution SAR calibration like TerraSAR X[8]. In this paper, a new ARC based on FPGA range delay system is introduced. Each range delay point has its owned independent delay interval. It’s easy to set the current delay to avoid ground inhomogeneous or bright target. In the following section, basic ARC theory and design concept will be introduced. Section 3 shows a FPGA based ARC system. Finally, field test results and performance comparison will be given. ARC Basic and Design Concept ARC is designed to provide strong and clean pointwise target response signal for SAR geometric and radiometric calibrations. Figure 1 Range delay ARC block diagram Referred to Figure 1, the received power due to backscattering by an ARC of radar cross section σARC is given by [1] ) 1 ( ) 4 ( 4 3 2 ARC r t t r R G G P P σ π λ = where Pt is the transmitted power, and Gt and Gr are the transmit and receive antenna gains in the direction of the ARC. Figure 1 shows a basic range delay type ARC configuration block diagram. According to the radar equation, σARC is given as